IEC 60749-26:2006

Establishes a standard procedure for testing and classifying semiconductor devices according to their susceptibility to damage or degradation by exposure to a defined human body model electrostatic discharge. The objective is to provide reliable, repeatable test results so that accurate classifications can be performed. The testing shall be selected from this test method or the machine model test method (see IEC 60749-27).

IEC 60749-26:2013 establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. ESD testing of semiconductor devices is selected from this test method, the machine model (MM) test method (see IEC 60749-27) or other ESD test methods in the IEC 60749 series. The HBM and MM test methods produce similar but not identical results; unless otherwise specified, this test method is the one selected. This edition includes the following significant technical changes with respect to the previous edition: a) descriptions of oscilloscope and current transducers have been refined and updated; b) the HBM circuit schematic and description have been improved; c) the description of stress test equipment qualification and verification has been completely re-written; d) qualification and verification of test fixture boards has been revised; e) a new section on the determination of ringing in the current waveform has been added; f) some alternate pin combinations have been included; g) allowance for non-supply pins to stress to a limited number of supply pin groups (associated non-supply pins) and allowance for non-supply to non-supply (i.e., I/O to I/O) stress to be limited to a finite number of 2 pin pairs (coupled non-supply pin pairs); h) explicit allowance for HBM stress using 2 pin HBM testers for die only shorted supply groups.